Art

J-GLOBAL ID：200902194118535147   Reference number：01A0172545

VLSI Design and CAD Algorithms. WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement.

WSSA 高性能シミュレーテッドアニーリングとトランジスタ配置への応用

Author (4)： SAIKA S (Matsushita Electric Industrial Co. Ltd., Kyoto-fu, JPN) ,  FUKUI M (Matsushita Electric Industrial Co. Ltd., Kyoto-fu, JPN) ,  TOYONAGA M (Matsushita Electric Industrial Co. Ltd., Kyoto-fu, JPN) ,  AKINO T (Kinki Univ., Wakayama, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E83-A  Issue： 12  Page： 2584-2591  Publication year： Dec. 25, 2000 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： LSI ,...

   To see more with JDream III (charged).   {{ this.onShowAbsJLink("http://jdream3.com/lp/jglobal/index.html?docNo=01A0172545&from=J-GLOBAL&jstjournalNo=F0699C") }}

JST classification (2)： General  (NC03161C) ,  CAD,CAM  (JE10000A)

Reference (13)：

• KIRKPATRICK, S. Optimization by simulated annealing. Science. 1983, 220, 4598, 671-680
• METROPOLIS, N. Equation of state calculations by fast computing machine. J. Chem. Phys. 1953, 21, 6, 1087-1092
• SECHEN, C. VLSI Placement and Global Routing Using Simulted Annealing. 1988
• MALLELA, S. Clustering based simulated annealing for standard cell placement. DAC. 1988, 312-317
• GLOVER, L. K. Standard cell placement using simulated sintering. DAC. 1987, 56-59

Terms in the title (4)： 高性能 ,  シミュレーテッドアニーリング ,  トランジスタ ,  応用