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J-GLOBAL ID：200902199063211772   Reference number：97A0644198

Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching.

トレースキャッシュ 広帯域幅命令フェッチへの低遅延アプローチ
Author (3)：
ROTENBERG E

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(Univ. Wisconsin-Madison)

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, 
BENNETT S

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(Intel Corp.)

About Intel Corp.

, 
SMITH J E

About SMITH J E

(Univ. Wisconsin-Madison)

About Univ. Wisconsin-Madison


Material：
Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture  (MICRO)

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Volume： 29th  Page： 24-34  Publication year： 1996 
JST Material Number： W0960A  ISSN： 1072-4451  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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pipeline processing

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,...
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JST classification (1)：
JST classification
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Control systems 
(JC02030K)

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Terms in the title (5)：
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トレース

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, 
キャッシュ

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, 
帯域幅

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, 
命令フェッチ

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, 
低遅延

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