Art

J-GLOBAL ID：200902221668491004   Reference number：06A0906345

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

動的差動論理に基づく低電力四値フリップフロップの設計

Author (3)： MOCHIZUKI Akira (Tohoku Univ., Sendai-shi, JPN) ,  SHIRAHAMA Hirokatsu (Tohoku Univ., Sendai-shi, JPN) ,  HANYU Takahiro (Tohoku Univ., Sendai-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E89-C  Issue： 11  Page： 1591-1597  Publication year： Nov. 01, 2006 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *many-valued logic ,...
Semi thesaurus term： current mode logic

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JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Logic circuits  (NC05070B)

Reference (24)：

• CHANDRAKASAN, A. Design of High-Performance Microprocessor Circuits. 2000
• BAKER, R. J. CMOS, Circuit Design, Layout, and Simulation. 2005
• CHEN, W. The VLSI Handbook. 2000
• KOZU, S. A 100MHz, 0.4W RISC processor with 200MHz multiply adder, using pulse-register technique. IEEE International Solid-State Circuits Conference, 1996. 1996, 40-41
• STAN, M. R. Power-aware computing. Computer. 2003, 36, 12, 35-38

Terms in the title (5)： 差動 ,  論理 ,  低電力 ,  フリップフロップ ,  設計