Art

J-GLOBAL ID：200902266826173981   Reference number：09A0577705

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures

アレイ型アーキテクチャに対する相互接続を意識したパイプライン合成

Author (5)： GAO Shanghua (Univ. of Tokyo, Tokyo, JPN) ,  YOSHIDA Hiroaki (Univ. of Tokyo, Tokyo, JPN) ,  SETO Kenshu (Univ. of Tokyo, Tokyo, JPN) ,  KOMATSU Satoshi (Univ. of Tokyo, Tokyo, JPN) ,  FUJITA Masahiro (Univ. of Tokyo, Tokyo, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E92-A  Issue： 6  Page： 1464-1475  Publication year： Jun. 01, 2009 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： submicron process ,  interconnection ,  delay ,  VLSI ,  CAD ,  *circuit synthesis ,  loop ,  application program ,  pipeline processing ,  parallel processing ,  concurrent processing ,  data transfer ,  scheduling ,  performance evaluation ,  improvement ,  experiment ,  *system architecture ,  array circuit
Semi thesaurus term： wire delay ,  performance improvement ,  evaluation experiment ,  deep submicron process

JST classification (1)： CAD,CAM  (JE10000A)

Reference (23)：

• CONG, J. Architecture-level synthesis for automatic interconnect pipelining. Proc. IEEE Design Automation Conf., 2004. 2004
• Semiconductor Industry Association. International Technology Roadmap for Semiconductors. 2003
• XU, M. Layout-driven high level synthesis for fpga based architectures. Proc. ACM Conf. on Design, Automation and Test in Europe, 1998. 1998, 446-450
• MOSHNYAGA, V. G. A floorplan based methodology for data-path synthesis of sub-micron asics. IEICE Trans. Inf. & Syst., D. 1996, E79, 10, 1389-1395
• KANG, D. Layout-driven architecture synthesis for high-speed digital filters. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2006, 14, 2, 203-207

Terms in the title (5)： アレイ ,  アーキテクチャ ,  相互接続 ,  意識 ,  パイプライン