Modeling and Simulation of Via-Connected Power Bus Stacks in Multilayer PCBs

WANG Zhi Liang; WANG Zhi Liang; WADA Osami; HARADA Takashi; YAGUCHI Takahiro; TOYOTA Yoshitaka; KOGA Ryuji

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J-GLOBAL ID：200902275855222575 Reference number：05A0681652

Modeling and Simulation of Via-Connected Power Bus Stacks in Multilayer PCBs

多層PCBにおけるビア接続電力バススタックのモデル化とシミュレーション

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Material：
Volume： E88-B Issue： 8 Page： 3176-3181 Publication year： Aug. 01, 2005
JST Material Number： L1369A ISSN： 0916-8516 Document type： Article
Article type：原著論文 Country of issue： Japan (JPN) Language： ENGLISH (EN)

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Noise measurement , Printed circuits

Reference (13)：

LEE, K. Modeling and analysis of multichip module power supply planes. IEEE Trans. Compon. Packag. Manuf. Technol. B. 1995, 18, 4, 628-639
ARCHAMBEAULT, B. Electrical package modeling including voltage and ground reference planes using the partial element equivalent circuit (PEEC) method. Proc. 13th Int. Zurich Symp. Electromagn. Compat., Zurich. Switzerland, Feb. 1999. 1999
FAN, J. DC power-bus modeling and design with a mixed-potential integral-equation formulation and circuit extraction. IEEE Trans. Electromagn. Compat. 2001, 43, 4, 426-436
YE, X. DC power-bus design using FDTD modeling with dispersive media and surface mount technology components. IEEE Trans. Electromagn. Compat. 2001, 43, 4, 579-587
LEI, C.-T. High-frequency characterization of power/ground plane structures. IEEE Trans. Microw. Theory Tech. 1999, 47, 5, 562-569

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