Art

J-GLOBAL ID：200902278674127340   Reference number：06A0362001

Proposal of Testable Multi-Context FPGA Architecture

試験可能な複数コンテキストFPGAアーキテクチャの提案

Author (2)： NAMBA Kazuteru (Chiba Univ., Chiba-shi, JPN) ,  ITO Hideo (Chiba Univ., Chiba-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E89-D  Issue： 5  Page： 1687-1693  Publication year： May. 01, 2006 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *FPGA ,...
Semi thesaurus term： overhead cost

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JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (16)：

• BROWN, S. D. Field-Programmable Gate Arrays. 1992
• WAUGH, T. C. Field programmable gate array key to reconfigurable array outperforming supercomputers. Proc. IEEE Custom Integrated Circuits Conf., 1991. 1991, 661-664
• BROWN, J. DELTA : Prototype for a first-generation dynamically programmable gate array. 1995
• TRIMBERGER, S. A time-multiplexed FPGA. IEEE Symp. Field-Programmable Custom Comp. Machines, April 1997. 1997, 22-28
• STROUD, C. E. A Designer's Guide to Built-In Self-Test. 2002

Terms in the title (5)： 試験 ,  コンテキスト ,  FPGA ,  アーキテクチャ ,  提案