Art

J-GLOBAL ID：201002209256040530   Reference number：10A0135367

An analysis of interference in synchronous systems

同期システムにおける干渉の解析

Author (2)： YOSHIMURA Tsutomu (High Frequency and Optical Devices Works, Mitsubishi Electric Corp.) ,  IWATA Atsushi (Graduate School of Advanced Sciences of Matter, Hiroshima Univ.)
Material： IEICE Electronics Express (Web)  (IEICE Electron Express (Web))
Volume： 1  Issue： 15  Page： 465-471 (J-STAGE)  Publication year： 2004 
JST Material Number： U0039A  ISSN： 1349-2543  Document type： Article
Article type： 短報  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *jitter ,  phase noise ,  interference noise ,  MOS integrated circuit ,  CMOS structure ,  frequency synchronization ,  phase locking ,  *phase locked loop ,  VCO ,  MOS structure

JST classification (1)： Electronic circuits in general  (NC05010N)

Reference (5)：

• [1] B. Razavi, “A study of injection locking and pulling in oscillators, ” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sept. 2004.
• [2] W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, UK, 1998.
• [3] M. Nagata, J. Nagai, K. Hijikawa, T. Morie, and A. Iwata, “Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits, ” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 539-549, March 2001.
• [4] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators, ” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
• [5] W. F. Egan, <i>Phase-Lock Basics</i>, John Wiley & Sons, Inc., NY, 1998.

Terms in the title (2)： 干渉 ,  解析