Art
J-GLOBAL ID:201002230697980847   Reference number:10A0874808

A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips

マルチプロセッサシステムオンチップにおけるハードウェアおよびソフトウェアコンポーネントのための統一性能推定手法
Author (4):
Material:
Volume:Page: 194-206 (J-STAGE)  Publication year: 2010 
JST Material Number: U0110A  ISSN: 1882-6687  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: ENGLISH (EN)
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Semi thesaurus term:
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.

JST classification (2):
JST classification
Category name(code) classified by JST.
Special-purpose arithmetic and control units  ,  Digital computer systems in general 
Reference (24):
  • 1) Martin, G.: Overview of the MPSoC Design Challenge, Proc. DAC' 06, pp.274-279 (2006).
  • 2) Isshiki, T., et al.: Trace-Driven Workload Simulation Method for Multiprocessor System-On-Chips, Proc. DAC '09, pp.232-237 (2009).
  • 3) Wunderlich, R., et al.: SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, Proc. 30th ISCA, pp.84-97 (2003).
  • 4) Sherwood, T., et al.: Automatically Characterizing Large Scale Program Behavior, Proc. ASPLOS-X, pp.45-57 (2002). (distributed to authors).
  • 5) Szwed, P.K., et al.: SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing, Proc. INTERACT-8, pp.65-74 (2004).
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