Art

J-GLOBAL ID：201002270371650067   Reference number：10A0612214

A Signal Detection Circuit for 8b/10b 2.5 Gb/s Serial Data Communication System in 90 nm CMOS

90nmCMOSにおける8b/10b 2.5Gb/sシリアルデータ通信システムに対する信号検出回路

Author (4)： SASAKI Kozue (Tokyo Univ. Sci., Noda-shi, JPN) ,  SATO Hiroki (Tokyo Inst. of Technol., Tokyo, JPN) ,  HYOGO Akira (Tokyo Univ. Sci., Noda-shi, JPN) ,  SEKINE Keitaro (Tokyo Univ. Sci., Noda-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E93-C  Issue： 6  Page： 864-866  Publication year： Jun. 01, 2010 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 短報  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： semiconductor ,  *data communication ,  *signal detection ,  circuit ,  printed board ,  data ,  temperature ,  full wave rectification ,  edge detection ,  sample holding circuit ,  *complementary metal oxide semiconductor
Semi thesaurus term： serial communication ,  back plane

JST classification (2)： Modulator and demodulator circuits  (NC05050F) ,  Semiconductor integrated circuit  (NC03162T)

Reference (4)：

• LEE, J. A 20-Gb/s adaptive equalizer in 0.13-μm CMOS technology. IEEE J. Solid-State Circuits. 2006, 41, 9, 2058-2066
• SUN, R. A low-power, 20-Gb/s continuous-time adaptive passive equalizer. IEEE International Symposium on Circuit and Systems, May 2005. 2005, 920-923
• CHOI, J.-S. A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method. IEEE J. Solid-State Circuits. 2004, 39, 3, 419-425
• GONDI, S. A 10-Gb/s CMOS adaptive equalizer for backplane applications. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005. 2005, 328-329

Terms in the title (2)： データ通信システム ,  信号検出回路