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J-GLOBAL ID:201102276138267577   Reference number:11A1585985

A Hypothesis Verification Method Using Regression Tree for Semiconductor Yield Analysis

半導体歩留り解析のための回帰木に基づく仮説検証手法の提案
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Volume: 131  Issue: 10  Page: 1232-1239 (J-STAGE)  Publication year: 2011 
JST Material Number: X0451A  ISSN: 0913-6339  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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Manufacturing technology of solid-state devices  ,  Statistical quality control 
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