Art

J-GLOBAL ID：201202294262010180   Reference number：12A0607972

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition

HMMに基づく孤立単語認識における出力確率および尤度スコア計算に対する多重高速保存型一括並列処理によるVLSIアーキテクチャ

Author (5)： NAKAMURA Kazuhiro (Graduate School of Information Sci. Nagoya Univ.) ,  SHIMAZAKI Ryo (Graduate School of Information Sci. Nagoya Univ.) ,  YAMAMOTO Masatoshi (Graduate School of Information Sci. Nagoya Univ.) ,  TAKAGI Kazuyoshi (Graduate School of Informatics, Kyoto Univ.) ,  TAKAGI Naofumi (Graduate School of Informatics, Kyoto Univ.)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E95-C  Issue： 4  Page： 456-467 (J-STAGE)  Publication year： 2012 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： recognition ,  Probability ,  *parallel processing ,  micro circuit technique ,  *hidden Markov model ,  register ,  vector (mathematics) ,  conservation ,  likelihood
Semi thesaurus term： hidden Markov model ,  *VLSI architecture ,  architecture ,  stream processing ,  processing time ,  *word recognition

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (8)：

• [1] R. Shimazaki, K. Nakamura, M. Yamamoto, K. Takagi, and N. Takagi, “A High-speed VLSI Architecture of Output Probability and Likelihood Score Computation for HMM-based Recognition Systems,” Proc. Workshop on Synthesis and System Integration of Mixed Technologies 2010, pp.42-47, 2010.
• [2] B. Mathew, A. Davis, and Z. Fang, “A low-power accelerator for the SPHINX 3 speech recognition system,” Proc. Int'l Conf. on Compilers, Architecture and Synthesis for Embedded Systems, pp.210-219, 2003.
• [3] H. Noguchi, K. Miura, T. Fujinaga, T. Sugahara, H. Kawaguchi, and M. Yoshimoto, “VLSI architecture of GMM processing and Viterbi decoder for 60,000-word real-time continuous speech recognition,” IEICE Trans. Electron., vol.E94-C, no.4, pp.458-467, April 2011.
• [4] Y. Kim and H. Jeong, “A systolic FPGA architecture of two-level dynamic programming for connected speech recognition,” IEICE Trans. Inf. & Syst., vol.E90-D, no.2, pp.562-568, Feb. 2007.
• [5] S. Yoshizawa, N. Wada, N. Hayakawa, and Y. Miyanaga, “Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system,” IEEE Trans. Circuits Syst., vol.53, no.1, pp.70-77, 2006.

Terms in the title (10)： HMM ,  単語認識 ,  確率 ,  尤度 ,  スコア ,  計算 ,  多重 ,  保存 ,  並列処理 ,  VLSIアーキテクチャ