Art

J-GLOBAL ID：201302275095070063   Reference number：13A1793936

A Test Compaction Oriented Don’t Care Identification Method Based on X-bit Distribution

Xビット分布に基づく試験圧縮指向ドントケア同定法

Author (4)： YAMAZAKI Hiroshi (Graduate School of Industrial Technol., Nihon Univ.) ,  WAKAZONO Motohiro (Graduate School of Industrial Technol., Nihon Univ.) ,  HOSOKAWA Toshinori (Coll. of Industrial Technol., Nihon Univ.) ,  YOSHIMURA Masayoshi (Dep. of Computer Sci. and Communication Engineering, Kyushu Univ.)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E96-D  Issue： 9  Page： 1994-2002 (J-STAGE)  Publication year： 2013 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： test ,  compression ,  *identification ,  VLSI ,  *test pattern ,  circuit ,  quality ,  model ,  improvement
Semi thesaurus term： x-filling ,  benchmark circuit ,  failure model

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (15)：

• [1] H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985.
• [2] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1995.
• [3] J. Ferguson and J. Shen, Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis, International Test Conference, pp.475-484, 1988.
• [4] M. Renovell, P. Huc, and Y. Bertrand, “The concept of resistance interval: A new parametric model for realistic resistive bridging fault,” 13th IEEE VLSI Test Symposium, pp.184-189, 1995.
• [5] T.M. Storey and W. Maly, CMOS Bridging Fault Detection, International Test Conference, pp.842-851, 1990.

Terms in the title (4)： ビット ,  分布 ,  試験 ,  同定法