Art

J-GLOBAL ID：201302290146710819   Reference number：13A1793928

Neighborhood Level Error Control Codes for Multi-Level Cell Flash Memories

マルチレベルセルフラッシュメモリに対する隣接レベル誤り制御符号

Author (2)： KOTAKI Shohei (Graduate School of Advanced Integration Sci., Chiba Univ.) ,  KITAKAMI Masato (Graduate School of Advanced Integration Sci., Chiba Univ.)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E96-D  Issue： 9  Page： 1926-1932 (J-STAGE)  Publication year： 2013 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： memory element ,  *flash memory ,  coding(signal) ,  error(mistake) ,  asymmetry ,  symbol ,  *error detection ,  code ,  Hamming code ,  error correcting code ,  transmission characteristic
Semi thesaurus term： *NAND flash memory ,  error-free ,  memory cell ,  error control coding

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Signal theory  (ND02020G)

Reference (16)：

• [1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory,” Proc. IEEE, vol.91, no.4, pp.489-502, April 2003.
• [2] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM and flash EEPROM with NAND structure cell,” Electron Devices Meeting, 1987 International, vol.33, pp.552-555, 1987.
• [3] N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L.R. Nevill, “Bit error rate in NAND flash memories,” IEEE International Reliability Physics Symposium, pp.9-19, 2008.
• [4] Y. Cai, E.F. Haratsch, O. Mutlu, and K. Mai, “Error patterns in MLC NAND flash memory: Measurement, characterization, and analysys,” Design, Automation & Test in Europe Conference & Exhibition, pp.521-526, March 2012.
• [5] Y. Maeda and H. Kaneko, “Error control coding for multilevel cell flash memories using nonbinary low-density parity-check codes,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.367-375, 2009.

Terms in the title (2)： 誤り制御 ,  符号