Art

J-GLOBAL ID：201402259023344098   Reference number：14A0775753

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

非同期多チップNoCに対する高スループット部分並列チップ間リンクアーキテクチャ

Author (6)： ONIZAWA Naoya (Frontier Res. Inst. for Interdisciplinary Sciences, Tohoku Univ.) ,  MOCHIZUKI Akira (Res. Inst. of Electrical Communication, Tohoku Univ.) ,  SHIRAHAMA Hirokatsu (Res. Inst. of Electrical Communication, Tohoku Univ.) ,  IMAI Masashi (Dept. of Electronics and Information Technol., Hirosaki Univ.) ,  YONEDA Tomohiro (National Inst. of Informatics) ,  HANYU Takahiro (Res. Inst. of Electrical Communication, Tohoku Univ.)
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E97.D  Issue： 6  Page： 1546-1556 (J-STAGE)  Publication year： 2014 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *VLSI ,  *throughput ,  computer architecture ,  *link ,  input-output ,  mode ,  signal transmission ,  crosstalk(interaction) ,  power supply
Semi thesaurus term： *NoC ,  data transmission ,  burst mode ,  *high throughput ,  Parallel architecture

JST classification (3)： Hydrid integrated circuit  (NC03163K) ,  Special-purpose arithmetic and control units  (JC04030Y) ,  Communication network  (ND07030A)

Reference (32)：

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• [3] N. Onizawa, A. Matsumoto, T. Funazaki, and T. Hanyu, “High-throughput compact delay-insensitive asynchronous NoC router,” IEEE Trans. Comput., vol.63, no.3, pp.637-649, 2014.
• [4] L. Plana, J. Bainbridge, S. Furber, S. Salisbury, Y. Shi, and J. Wu, “An on-chip and inter-chip communications network for the SpiNNaker massively-parallel neural net simulator,” Second ACM/IEEE International Symposium on Networks-on-Chip, pp.215-216, April 2008.
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Terms in the title (5)： 非同期 ,  NoC ,  高スループット ,  リンク ,  アーキテクチャ