Art

J-GLOBAL ID：201402270996459801   Reference number：14A0409097

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors

再構成可能データパスプロセッサのためのNb9層構造に基づいた大規模集積回路設計

Author (12)： FUJIMAKI Akira (Nagoya Univ.) ,  TANAKA Masamitsu (Nagoya Univ.) ,  KASAGI Ryo (Nagoya Univ.) ,  TAKAGI Katsumi (Nagoya Univ.) ,  OKADA Masakazu (Nagoya Univ.) ,  HAYAKAWA Yuhi (Nagoya Univ.) ,  TAKATA Kensuke (Nagoya Univ.) ,  AKAIKE Hiroyuki (Nagoya Univ.) ,  YOSHIKAWA Nobuyuki (Yokohama National Univ.) ,  NAGASAWA Shuichi (AIST) ,  TAKAGI Kazuyoshi (Kyoto Univ.) ,  TAKAGI Naofumi (Kyoto Univ.)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E97-C  Issue： 3  Page： 157-165 (J-STAGE)  Publication year： 2014 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *data pass ,  *niobium ,  *LSI ,  flux quantum ,  Josephson junction ,  critical current density ,  yield(ratio) ,  logic element ,  floating point arithmetic ,  arithmetic processor
Semi thesaurus term： RSFQ ,  *reconfigurable data path ,  arithmetic and logic unit ,  logic gate

JST classification (2)： Josephson junction and elements  (BM04043E) ,  General  (NC03161C)

Reference (36)：

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Terms in the title (5)： 再構成可能データパス ,  プロセッサ ,  層構造 ,  大規模集積回路 ,  設計