Art

J-GLOBAL ID：201402270996459801   Reference number：14A0409097

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors

再構成可能データパスプロセッサのためのNb9層構造に基づいた大規模集積回路設計

Author (12)： FUJIMAKI Akira (Nagoya Univ.) ,  TANAKA Masamitsu (Nagoya Univ.) ,  KASAGI Ryo (Nagoya Univ.) ,  TAKAGI Katsumi (Nagoya Univ.) ,  OKADA Masakazu (Nagoya Univ.) ,  HAYAKAWA Yuhi (Nagoya Univ.) ,  TAKATA Kensuke (Nagoya Univ.) ,  AKAIKE Hiroyuki (Nagoya Univ.) ,  YOSHIKAWA Nobuyuki (Yokohama National Univ.) ,  NAGASAWA Shuichi (AIST) ,  TAKAGI Kazuyoshi (Kyoto Univ.) ,  TAKAGI Naofumi (Kyoto Univ.)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E97-C  Issue： 3  Page： 157-165 (J-STAGE)  Publication year： 2014 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *data pass ,  *niobium ,  *LSI ,  flux quantum ,  Josephson junction ,  critical current density ,  yield (ratio) ,  logic element ,  floating point arithmetic ,  arithmetic processor ,  arithmetic and logic unit
Semi thesaurus term： RSFQ ,  *reconfigurable data path ,  logic gate

JST classification (2)： Josephson junction and elements  (BM04043E) ,  General  (NC03161C)

Reference (36)：

• [1] K. Nakajima, Y. Onodera, and Y. Ogawa, “Logic design of Josephson network,” J. Appl. Phys., vol.47, no.4, pp.1620-1627, April 1976.
• [2] K.K. Likharev and V.K. Semenov, “RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,” IEEE Trans. Appl. Supercond., vol.1, no.1, pp.3-28, March 1991.
• [3] M. Dorojevets, P. Bunyk, and D. Zinoviev, “FLUX chip: Design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-µm LTS technology,” IEEE Trans. Appl. Supercond., vol.11, no.1, pp.326-332, March 2001.
• [4] M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, A. Fujimaki, H. Hayakawa, N. Yoshikawa, H. Terai, and S. Yorozu, “A single-flux-quantum logic prototype microprocessor,” 2004 IEEE Int. Solid-State Circuits Conf. (ISSCC 2004) Digest of Technical Papers, no.16.7, pp.298, San Francisco, USA, Feb. 2004.
• [5] M. Tanaka, T. Kondo, N. Nakajima, T. Kawamoto, Y. Yamanashi, Y. Kamiya, A. Akimoto, A. Fujimaki, H. Hayakawa, N. Yoshikawa, H. Terai, Y. Hashimoto, and S. Yorozu, “Demonstration of a single-flux-quantum microprocessor using passive transmission lines,” IEEE Trans. Appl. Supercond., vol.15, no.2, pp.400-404, June 2005.

Terms in the title (5)： 再構成可能データパス ,  プロセッサ ,  層構造 ,  大規模集積回路 ,  設計