Art

J-GLOBAL ID：201502220131180217   Reference number：15A1150381

The Network-on-Chip Optimization By Using Of Genetic Algorithm

GAを用いたNoCの最適設計探索

Author (2)： MURAKAMI DAICHI (東大) ,  HIRAKI KEI (東大)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 115  Issue： 174(CPSY2015 16-44)  Page： 1-6  Publication year： Jul. 28, 2015 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： *genetic algorithm ,  *VLSI ,  heterogeneous system ,  queuing time ,  optimum design ,  network structure ,  layout design ,  *optimization ,  network ,  complex system ,  simulation
Semi thesaurus term： *GA ,  *NoC ,  network simulation ,  telecommunication network topology ,  latency time ,  heterogeneous system ,  *layout optimization ,  complexity network

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Computer networks  (JC03000K)

Reference (3)：

• Asit K. Mishra, N. Vijaykrishnan, and Chita R. Das. A Case for Heterogeneous On-Chip Interconnects for CMPs. International Symposium on Computer Architecture, pages 69-80, 2011.
• Ahmed A. Margan, Haytham Elmiligi, M. Watheq El-Kharashi, and Fayez Gebali. Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithm. IEEE International Symposium on Circuits and Systems, pages 3725-3728, 2010.
• Reetuparna Das, Statish Narayanasamy, Sudhir K. Satpathy and Ronald G. Dreslinski. Catnap: Energy Proportional Multiple Network-on-Chip. International Symposium on Computer Architecture, pages 320-331, 2013.

Terms in the title (4)： Ga ,  NOC ,  最適設計 ,  探索