Art

J-GLOBAL ID：201502221511303260   Reference number：15A0744456

Simulation of Electron Transport in Atomic Monolayer Semiconductor FETs

単原子層半導体FETにおける電子移動のシミュレーション

Author (5)： TSUCHIYA Hideaki (Dep. of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe Univ.) ,  TSUCHIYA Hideaki (CREST, Japan Sci. and Technol. Agency) ,  KANEKO Shiro (Dep. of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe Univ.) ,  MORI Noriyasu (Dep. of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe Univ.) ,  HIRAI Hideki (Dep. of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe Univ.)
Material： Journal of Advanced Simulation in Science and Engineering (Web)  (日本シミュレーション学会英文誌(Web))
Volume： 2  Issue： 1  Page： 127-152 (J-STAGE)  Publication year： 2015 
JST Material Number： U0612A  ISSN： 2188-5303  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *FET ,  MOSFET ,  *monoatomic layer ,  band gap ,  graphene ,  ribbon crystal ,  *electron transfer ,  effective mass ,  simulation ,  band structure ,  semiconductor material ,  silicon ,  nanostructure ,  tight binding approximation ,  Germanium ,  silicene ,  nanoribbon
Semi thesaurus term： germanium ,  tight binding approximation

JST classification (3)： Electric conduction in semiconductors and insulators in general  (BM03041P) ,  Electronic structure of crystalline semiconductors  (BM02060N) ,  Materials of solid-state devices  (NC03020K)

Reference (37)：

• [1] International Technology Roadmap for Semiconductors, http://www.itrs.net/, 2013.
• [2] C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, C. Hu: A comparative study of advanced MOSFET concepts, IEEE Trans. Electron Devices, 43:10 (1996) 1742-1753.
• [3] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, C. Hu: Ultrathin-body SOI MOSFET for deep-sub-tenth micron era, IEEE Electron Devices Lett., 21:5 (2000) 254-255.
• [4] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, C. Hu: FinFET - A self-aligned double-gate MOSFET scalable to 20 nm, IEEE Trans. Electron Devices, 47:12 (2000), 2320-2325.
• [5] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, D. Kyser: FinFET scaling to 10nm gate length, in Proc. 2002 Int’l Electron Devices Meeting (IEDM 2002), San Francisco, 2002, 251-254.

Terms in the title (4)： 単原子層 ,  FET ,  電子移動 ,  シミュレーション