2005 - 2006 Architecture and Design Method for High-Quality Hetero-Timing VLSI Systems
2002 - 2005 Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler
2000 - 2001 Performance analysis on hybrid parallel programming on SMP cluster system
1997 - 1999 Study on Asynchronous VLSI System Design Methodology
1992 - 1992 高性能コンピュータ設計を支援する方式レベル検証系の開発
1991 - 1991 高性能コンピュータ設計を支援する汎用方式シミュレータの開発
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Papers (169):
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura. ILP Based Mapping for Elastic CGRAs. 2023 IEEE 29th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). 2023
Hu, S., Kondo, M., He, Y., Sakamoto, R., Zhang, H., Zhou, J., Nakamura, H. An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. Microprocessors and Microsystems. 2023. 102
Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hiroki Kobayashi, et al. mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. Proc. the 8th IEEE International Conference on Cloud and Big Data Computing (CBDCom 2022). 2022. 1-7
Shresthamali, S., Kondo, M., Nakamura, H. Multi-Objective Resource Scheduling for IoT Systems Using Reinforcement Learning †. Journal of Low Power Electronics and Applications. 2022. 12. 4