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J-GLOBAL ID:201602216404584975   Reference number:16A1111407

I/O分割による遅延隠蔽を用いたOut-of-coreなGPU Set Intersectionの性能評価(Unrefereed Workshop Manuscript)

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Volume: 2016  Issue: HPC-155  Page: Vol.2016-HPC-155,No.3,1-7 (WEB ONLY)  Publication year: Aug. 01, 2016 
JST Material Number: U0451A  Document type: Proceedings
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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Control systems  ,  Special-purpose arithmetic and control units 
Reference (15):
  • Amossen, R. R. and Pagh, R.: A New Data Layout for Set Intersection on GPUs, Proceedings - 25th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2011, pp. 698-708 (2011).
  • Ao, N., Zhang, F., Wu, D., Stones, D. S., Wang, G., Liu, J. and Lin, S.: Efficient Parallel Lists Intersection and Index Compression Algorithms using Graphics Processing Units, Proceedings of the VLDB Endowment, Vol. 4, No. 8, pp. 470-481 (2011).
  • Bille, P., Pagh, A. and Pagh, R.: Fast Evaluation of Union-Intersection Expressions, Proceedings of the 18th International Conference on Algorithms and Computation (ISAAC’07), pp. 739-750 (2007).
  • Demaine, E. D., Ldpez-ortiz, A. and Munro, J. I.: Adaptive Set Intersections, Unions, and Differences, Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms (SODA’00), pp. 743-752 (2000).
  • Ding, B. and K, A. C.: Fast Set Intersection in Memory, Proceedings of the VLDB Endowment, Vol. 4, No. 4, pp. 255-266 (2011).
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