Art

J-GLOBAL ID：201602279366063838   Reference number：16A1366890

CMOS Majority Circuit with Large Fan-In

大規模ファンインを備えたCMOS多数決回路

Author (6)： AKIMA Hisanao (Research Institute of Electrical Communication, Tohoku University) ,  KATAYAMA Yasuhiro (Toshiba Corporation Semiconductor & Storage Products Company) ,  SAKURABA Masao (Research Institute of Electrical Communication, Tohoku University) ,  NAKAJIMA Koji (Research Institute of Electrical Communication, Tohoku University) ,  MADRENAS Jordi (Department of Electronic Engineering, Universitat Politecnica de Catalunya) ,  SATO Shigeo (Research Institute of Electrical Communication, Tohoku University)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E99.C  Issue： 9  Page： 1056-1064(J-STAGE)  Publication year： 2016 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *large scale ,  *number ,  semiconductor ,  fault tolerance ,  threshold logic ,  spectral diffusion ,  coding (signal) ,  neural network (biomodel) ,  *majority logic ,  transistor ,  SPICE program ,  simulation ,  yield (ratio) ,  complementary metal oxide semiconductor ,  *fan in ,  Monte Carlo simulation
Semi thesaurus term： HSPICE ,  fault tolerant ,  artificial neural network ,  majority voting

Author keywords (4)： majority logic ,  MOS analog circuits ,  nonlinear circuits ,  Monte Carlo simulation

JST classification (1)： Logic circuits  (NC05070B)

Reference (16)：

• [1] S.B. Akers, “Synthesis of combinational logic using three-input majority gates,” Proc. 3rd Ann. Symp. on Switching Circuit Theory and Logical Design, pp.149-157, Oct. 1962.
• [2] H. Özdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. Çilingiroğlu, “A capacitive threshold-logic gate,” IEEE J. Solid-State Circuits, vol.31, no.8, pp.1141-1150, Aug. 1996.
• [3] K. Kobayashi, K. Yamamoto, H. Kokubun, and K. Kobayashi, “A 50 MHz CMOS pipelined majority logic decoder for (1057, 813) difference-set cyclic code,” IEICE Trans. Fundamentals, vol.E79-A, no.7, pp.1060-1067, July 1996.
• [4] T. Maseng, “Performance analysis of a majority logic multiplex system,” IEEE Trans. Commun., vol.28, no.9, pp.1675-1680, Sept. 1980.
• [5] A. Sugiura and M. Inatsu, “An amplitude limiting CDM by using majority logic,” IEICE Trans. Fundamentals, vol.E80-A, no.2, pp.346-348, Feb. 1997.

Terms in the title (4)： 大規模 ,  ファンイン ,  CMOS ,  多数決