Art

J-GLOBAL ID：201702213468613350   Reference number：17A0980551

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage

重大エリア意識重みづけ故障カバレッジを考慮したリ置換に基づくテストパターン削減

Author (2)： ARAI Masayuki (College of Industrial Technology, Nihon University) ,  IWASAKI Kazuhiko (Library and Information Center, Tokyo Metropolitan University)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E100.A  Issue： 7  Page： 1488-1495(J-STAGE)  Publication year： 2017 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *manufacturing ,  weighting ,  *coverage factor ,  *test pattern ,  *automatic test ,  cost reduction ,  computer algorithm ,  *integrated circuit
Semi thesaurus term： *fault coverage ,  *semiconductor device manufacture ,  greedy algorithm

Author keywords (6)： weighted fault coverage ,  critical area ,  test cost reduction ,  test pattern reduction ,  bridge fault ,  open fault

JST classification (2)： General  (NC03161C) ,  Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (27)：

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• [2] D. Gizopoulos ed., Advances in Electronic Testing: Challenges and Methodologies, Springer, 2007.
• [3] S.C. Ma, P. Franco, and E.J. McCluskey, “An experimental chip to evaluate test techniques experiment results,” International Test Conference, pp.663-672, 1995. 10.1109/test.1995.529895
• [4] B. Benware, C. Schuermyer, N. Tamarapalli, K.-H. Tsai, S. Ranganathan, R. Madge, and P. Krishnamurthy, “Impact of multiple-detect test patterns on product quality,” International Test Conference, pp.1031-1040, 2003. 10.1109/test.2003.1271091
• [5] K.Y. Cho, S. Mitra, and E.J. McCluskey, “Gate exhaustive testing,” International Test Conference, Paper 31.3, 2005. 10.1109/test.2005.1584040

Terms in the title (6)： エリア ,  意識 ,  重みづけ ,  故障カバレッジ ,  置換 ,  テストパターン