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J-GLOBAL ID:201702220451324909   Reference number:17A1942854

Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking

Face-down積層型3次元FPGAの性能評価
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Volume: 117  Issue: 279(RECONF2017 37-49)  Page: 31-36  Publication year: Oct. 30, 2017 
JST Material Number: S0532B  ISSN: 0913-5685  Document type: Proceedings
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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Digital computer hardwares in general 
Reference (14):
  • M. J. Alexander, J. P. Cohoon, J. L. Colflesh, J. Karro, G. Robins, and C. Science, “Three-Dimensional Field-Programmable Gate Arrays,” Proc. of the Eighth Annual IEEE International, pp.253-256, Sept. 1995
  • K. Siozios, V. F. Pavlidis, and D. Soudris, “A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric,” ACM Tran. on Reconfigurable Technology and Systems, Vol. 5, No. 1, Article 4, Mar. 2012.
  • A. Gayasen, V. Narayanan, M. Kandemir, and A. Rahman, “Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues,” IEEE Tran. on Very Large Scale Integration (VLSI) Systems, vol.16, no.7, pp.882-893, July 2008.
  • M.Amagasaki, Q.Zhao, M.Iida, M.Kuga and T.Sueyoshi, “A 3D FPGA Architecture to Realize Simple Die Stacking”, IPSJ Transactions on System LSI Design Methodology, Vol.8, pp.116-122, Aug. 2015
  • Berkeley Logic Synthesis and Verification Group, “ABC: A System for Sequential Synthesis and Verification,” http://www.eecs.berkeley.edu/alanmi/abc/.
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