Art

J-GLOBAL ID：201702236163962179   Reference number：17A1942798

Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits

周辺論理回路の内部信号による確率変数生成

Author (5)： KUBOTA Naoya (Hiroshima City Univ.) ,  FUJIHA Maiki (Hiroshima City Univ., Hiroshima, JPN) ,  ICHIHARA Hideyuki (Hiroshima City Univ.) ,  IWAGAKI Tsuyoshi (Hiroshima City Univ.) ,  INOUE Tomoo (Hiroshima City Univ.)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 117  Issue： 274(DC2017 33-67)  Page： 115-120  Publication year： Oct. 30, 2017 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： variable ,  probability ,  *methodology ,  *random number generation ,  digital circuit ,  *logic circuit ,  area ,  soft error ,  semiconductor chip ,  algorithm
Semi thesaurus term： chip area ,  *probabilistic method ,  random variable

JST classification (1)： Logic circuits  (NC05070B)

Reference (9)：

• H. Ichihara, D. Sunamori, S. Ishii, T. Iwagaki and T. Inoue, ′′Compact and Accurate Stochastic Circuits with Shared Random Number Sources,′′ Proc. ICCD, pp. 361-366, Oct. 2014.
• N. Kubota, H. Ichihara, T. Iwagaki and T. Inoue, ′′Stochastic Number Generation with Internal Signals of Logic Circuits,′′ Proc. SASIMI, Oct. 2016.
• H. Ichihara, T. Sugino, S. Ishii, T. Iwagaki and T. Inoue, ′′Compact and Accurate Digital Filters Based on Stochastic Computing,′′ Trans. on Emerging Topics in Comp., pp. 1-1, Sep. 2016.
• S. C. Smithson, K. Boga, A. Ardakani, B. H. Meyer, and W. J. Gross, ′′Stochastic Computing Can Improve Upon Digital Spiking Neural Networks,′′ Proc. SiPS, pp. 309-314, Sep. 2016.
• I. Perez-Andrade, S. Zhong, R. Maunder, and B. Al-Hashimi, ′′Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs,′′ IEEE Access, vol.4, pp. 1008- 1038, 2016.

Terms in the title (3)： 周辺 ,  論理回路 ,  確率変数