Art

J-GLOBAL ID：201702254535858148   Reference number：17A0504105

An Error Correction Method for Neighborhood-Level Errors in NAND Flash Memories

NANDフラッシュメモリにおける隣接レベル誤りの誤り訂正法

Author (2)： KOTAKI Shohei (Graduate School of Advanced Integration Science, Chiba University) ,  KITAKAMI Masato (Graduate School of Advanced Integration Science, Chiba University)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E100.A  Issue： 2  Page： 653-662(J-STAGE)  Publication year： 2017 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *flash memory ,  error correcting code ,  error detection ,  *error correction ,  error rate ,  *queuing time ,  *throughput ,  improvement
Semi thesaurus term： *NAND flash memory ,  BER ,  durability enhancement

Author keywords (5)： error correcting codes ,  NAND Flash memories ,  multilevel cell ,  limited-magnitude errors ,  multipage programming

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (24)：

• [1] G. Dong, Y. Pan, N. Xie, C. Varanasi, and T. Zhang, “Estimating information-theoretical NAND flash memory storage capacity and its implication to memory system design space exploration,” IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst., vol.20, no.9, pp.1705-1714, 2012.
• [2] Y. Cai, E. Haratsch, O. Mutlu, and K. Mai, “Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis,” Design, Automation Test in Europe Conference Exhibition (DATE), pp.521-526, 2012.
• [3] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory,” Proc. IEEE, vol.91, no.4, pp.489-502, 2003.
• [4] F. Sun, S. Devarajan, K. Rose, and T. Zhang, “Design of on-chip error correction systems for multilevel NOR and NAND flash memories,” IET Circuits Devices Syst., vol.1, no.3, pp.241-249, June 2007.
• [5] Y. Cai, E.F. Haratsch, O. Mutlu, and K. Mai, “Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling,” Design, Automation Test in Europe Conference Exhibition (DATE), 2013, pp.1285-1290, March 2013.

Terms in the title (3)： NANDフラッシュメモリ ,  誤り ,  誤り訂正