Art

J-GLOBAL ID：201702278511259056   Reference number：17A0040921

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

組み立てたPCBにおけるオープン欠陥の電気的相互接続試験に対する内蔵テスト回路

Author (7)： Widiant (Institute of Technology and Science, Tokushima University) ,  HASHIZUME Masaki (Institute of Technology and Science, Tokushima University) ,  SUENAGA Shohei (Institute of Technology and Science, Tokushima University) ,  YOTSUYANAGI Hiroyuki (Institute of Technology and Science, Tokushima University) ,  ONO Akira (Kagawa National College of Technology) ,  LU Shyue-Kung (National Taiwan University of Science and Technology) ,  ROTH Zvi (Florida Atlantic University)
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E99.D  Issue： 11  Page： 2723-2733(J-STAGE)  Publication year： 2016 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *printed board ,  *defect ,  interconnection ,  *electric test ,  test structure ,  integrated circuit ,  part ,  inverter ,  electric current ,  time course ,  signal ,  simulation ,  prototyping ,  connection
Semi thesaurus term： *printed circuit board ,  *electrical test ,  built-in ,  test structure ,  IC ,  time variation

Author keywords (5)： electrical test ,  built-in test circuit ,  open defect ,  interconnect test ,  design for testability

JST classification (2)： Printed circuits  (NA05040O) ,  Electric and electronic parts in general  (NA05010H)

Reference (13)：

• [1] T. Sumimoto, T. Maruyamay, Y. Azuma, S. Goto, M. Mondo, N. Furukawa, and S. Okada, “Detection of Defects at BGA Solder Joints by Using X-ray Imaging,” IEEE Inter. Conf. On Industr. Tech., pp.238-241, 2002.
• [2] T. Sumimoto, T. Maruyama, Y. Azuma, S. Goto, M. Mondou, N. Furukawa, and S. Okada, “Detection of Defect of BGA by Tomography Imaging,” Journal of Systemics, Cybernetics and Informatics, vol.3 no.4, pp.10-14, 2005.
• [3] H. Bleeker, P. van den Eijnden, and F. de Jong, Boundary-scan Test: a Practical Approach, Kluwer Academic Publishers, 1993.
• [4] T. Sumimoto, J. Fang, Z. Wang, T. Maruyama, Y. Azuma, S. Goto, M. Mondou, N. Furukawa, and S. Okada, “Analysis of BGA Defects by Tomographic Images,” 6th Inter. Symp. on Instrum. and Contr. Tech., vol.6357, pp.1-5, 2006.
• [5] R.P. Cruz, “Flip Chip Advanced Package Solder Joint Embrittlement Fault Isolation Using TDR,” Proc. 5th Inter. Symp. on Qual. Electr. Design, pp.190-195, 2004.

Terms in the title (5)： PCB ,  欠陥 ,  相互接続 ,  試験 ,  テスト回路