Art

J-GLOBAL ID：201802219417553272   Reference number：18A1980188

Development of a Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply

単一電源を用いた低待機電力6トランジスタCMOS SRAMの開発

Author (2)： KOBAYASHI Nobuaki (Nihon University) ,  ENOMOTO Tadayoshi (Chuo University)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E101.C  Issue： 10  Page： 822-830(J-STAGE)  Publication year： 2018 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *complementary metal oxide semiconductor ,  *SRAM ,  electric power ,  *holding ,  *voltage ,  *adaptive control ,  *data reading ,  *data writing ,  electric power source equipment
Semi thesaurus term： gate voltage ,  data retention ,  word line ,  standby electricity consumption ,  Power Sources ,  *readout

Author keywords (6)： CMOS ,  SRAM ,  static-noise margin ,  standby power dissipation ,  leakage current ,  Self-controllable Voltage Level (SVL) circuit

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Memory units  (JC04060F)

Reference (11)：

• [1] C. Piguest, ed., Low-Power Electronics Design, pp.3.1-3.13, CRC Press, New York, 2004.
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• [5] R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, and F. Arnaud, “28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications,” IEEE Symposium on VLSI Circuits, pp.1-2, June 2016. 10.1109/vlsic.2016.7573512

Terms in the title (5)： 待機電力 ,  トランジスタ ,  CMOS ,  SRAM ,  開発