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J-GLOBAL ID：201802246073221761   Reference number：18A0656551

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA

FPGA上の二値化ディープニューラルネットワークの閾値ニューロンプルーニング

Author (3)： FUJII Tomoya (Department of Information and Communications Engineering, Tokyo Institute of Technology) ,  SATO Shimpei (Department of Information and Communications Engineering, Tokyo Institute of Technology) ,  NAKAHARA Hiroki (Department of Information and Communications Engineering, Tokyo Institute of Technology)
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E101.D  Issue： 2  Page： 376-386(J-STAGE)  Publication year： 2018 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *packaging(mounting) ,  *transformation and conversion ,  *neural network(biomodel) ,  *threshold ,  *neuron ,  *algorithm ,  memory(computer) ,  connection ,  convolution ,  learning ,  consumed electric power ,  power efficiency ,  embedded system
Semi thesaurus term： convolutional neural network ,  *FPGA Implementation ,  on-chip memory ,  *deep neural network ,  *pruning algorithm ,  memory access ,  *binarization ,  relearning

Author keywords (4)： machine learning ,  deep learning ,  pruning ,  FPGA

JST classification (3)： Digital computer systems in general  (JC02010O) ,  General  (NC03161C) ,  Artificial intelligence  (JE08000Z)

Reference (35)：

• [1] S. Anwar, K. Hwang, and W. Sung, “Structured pruning of deep convolutional neural networks,” Computer Research Repository (CoRR), Dec., 2015. https://arxiv.org/ftp/arxiv/papers/1512/1512.08571.pdf
• [2] Caffe: Deep learning framework, http://caffe.berkeleyvision.org/
• [3] Chainer: A powerful, flexible, and intuitive framework of neural networks, http://chainer.org/
• [4] S. Chakradhar, M. Sankaradas, V. Jakkula, and S. Cadambi, “A dynamically configurable coprocessor for convolutional neural networks,” Annual Int'l Symp. on Computer Architecture (ISCA), pp.247-257, 2010. 10.1145/1815961.1815993
• [5] The CIFAR-10 data set, http://www.cs.toronto.edu/~kriz/cifar.html

Terms in the title (4)： FPGA ,  二値化 ,  ディープニューラルネットワーク ,  閾値