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J-GLOBAL ID:201902215428514812   Reference number:19A1696644

ステンシル計算を対象としたメモリアクセスを最適化するラインバッファ自動挿入手法の検討

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Material:
Volume: 119  Issue: 18(RECONF2019 1-19)(Web)  Page: 11-16 (WEB ONLY)  Publication year: May. 02, 2019 
JST Material Number: S0532B  ISSN: 0913-5685  Document type: Proceedings
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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General-purpose arithmetic and control units  ,  Numerical computation 
Reference (10):
  • A. Sanaullah, R. Patel, and M. C. Herbordt. An empirically guided optimization framework for FPGA OpenCL. In In International Conference on Field Programmable Technology, pages 49-56, 2018.
  • Intel FPGA SDK for OpenCL Pro Edition: Best Practice Guide. https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807516407.html. Accessed: 2019/4/5.
  • J. Liu, J. Wickerson, and G. A. Constantinides. Loop splitting for efficient pipelining in high-level synthesis. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 72-79, 2016.
  • X. Gao, J. Wickerson, and G. A. Constantinides. Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-level Synthesis. In Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 234-243, 2016.
  • G. Roth, J. Mellor-Crummey, K. Kennedy, and R. G. Brickner. Compiling stencils in high performance Fortran. In SC ’97: Proceedings of the 1997 ACM/IEEE Conference on Supercomputing, pages 1-20, 1997.
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