Art
J-GLOBAL ID：201902219512747738
Reference number：19A1929143
A Study of Synchronization Methods in Modern GPUs
最新のGPUの同期方法の研究
Author (4)：
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Material：
Volume：
2019
Issue：
HPC-170
Page：
Vol.2019-HPC-170,No.21,1-6 (WEB ONLY)
Publication year：
Jul. 17, 2019
JST Material Number：
U0451A
Document type：
Proceedings
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
ENGLISH (EN)
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,
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,
,
Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
,
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JST classification (2)：
JST classification
Category name(code) classified by JST.
Control systems
, Special-purpose arithmetic and control units
Reference (11)：
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C. Nvidia, “Programming guide,” 2019.
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M. Harris et al., “Optimizing parallel reduction in cuda,” Nvidia developer technology, vol. 2, no. 4, p. 70, 2007.
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S. Tokui, K. Oono, S. Hido, and J. Clayton, “Chainer: a next-generation open source framework for deep learning,” in Proceedings of workshop on machine learning systems (LearningSys) in the twenty-ninth annual conference on neural information processing systems (NIPS), vol. 5, pp. 1-6, 2015.
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T. Sorensen, A. F. Donaldson, M. Batty, G. Gopalakrishnan, and Z. Rakamarić, “Portable inter-workgroup barrier synchronisation for gpus,” in ACM SIGPLAN Notices, vol. 51, pp. 39-58, ACM, 2016.
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S. Xiao and W.-c. Feng, “Inter-block gpu communication via fast barrier synchronization,” in 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), pp. 1-12, IEEE, 2010.
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Terms in the title
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