Art

J-GLOBAL ID：201902240985355752   Reference number：19A0106241

Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units

可逆加算器/減算器ブロックと算術論理ユニットの最小多重制御Toffoli回路のための機能設計

Author (4)： ALI Md Belayet (Department of Electrical Engineering and Computer Science, Iwate University) ,  HIRAYAMA Takashi (Department of Electrical Engineering and Computer Science, Iwate University) ,  YAMANAKA Katsuhisa (Department of Electrical Engineering and Computer Science, Iwate University) ,  NISHITANI Yasuaki (Department of Electrical Engineering and Computer Science, Iwate University)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E101.A  Issue： 12  Page： 2231-2243(J-STAGE)  Publication year： 2018 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *adder ,  *subtracter ,  *arithmetic processor ,  *logic circuit ,  *design ,  cost ,  circuit
Semi thesaurus term： *Toffoli gate ,  *function design ,  calculation cost ,  *ALU ,  *full adder ,  quantum circuit

Author keywords (7)： reversible function ,  reversible adder/subtractor ,  reversible arithmetic logic unit ,  incompletely-specified function ,  operation assignment ,  quantum cost ,  multiple-control Toffoli

JST classification (3)： Semiconductor integrated circuit  (NC03162T) ,  Logic circuits  (NC05070B) ,  Special-purpose arithmetic and control units  (JC04030Y)

Reference (43)：

• [1] M.K. Thomsen, R. Gluck, and H.B. Axelsen, “Reversible arithmetic logic unit for quantum arithmetic,” J. Phys. A: Math. Theor., vol.43, no.38, 2010. 10.1088/1751-8113/43/38/382002
• [2] M. Morrison and N. Ranganathan, “Design of reversible ALU based on novel programmable reversible logic gate structures,” IEEE Computer Society Annual Symposium on VLSI, pp.126-131, 2011. 10.1109/isvlsi.2011.30
• [3] R. Aradhaya, K.N. Muralidhara, and B. Kumar, “Design of low power arithmetic unit based on reversible logic,” International Journal of VLSI and Signal Processing Applications, vol.1, no.1, pp.30-38, 2011.
• [4] B.K. Sikdar, “Design of fault tolerant reversible arithmetic logic unit in QCA,” International Symposium on Electronic System Design, 2012. 10.1109/ised.2012.50
• [5] S. Sultan and K. Radecka, “Reversible architecture of computer arithmetic,” Int. J. Comput. Appl., vol.93, no.14, pp.6-14, May 2014. 10.5120/16281-5852

Terms in the title (5)： 加算器 ,  減算器 ,  算術論理ユニット ,  多重 ,  機能設計