Art

J-GLOBAL ID：201902263458755347   Reference number：19A1861392

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector

ループ遅延補償とADCベースサンプリング位相検出器を用いたタイプIディジタルリングベースPLL

Author (5)： XU Zule (The University of Tokyo) ,  FIRDAUZI Anugerah (Tokyo Institute of Technology) ,  MIYAHARA Masaya (High Energy Accelerator Research Organization) ,  OKADA Kenichi (Tokyo Institute of Technology) ,  MATSUZAWA Akira (Tokyo Institute of Technology)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E102.C  Issue： 7  Page： 520-529(J-STAGE)  Publication year： 2019 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *analog to digital converter ,  *demodulator ,  *phase locked loop ,  bandwidth ,  jitter ,  electric power consumption ,  semiconductor process ,  complementary metal oxide semiconductor ,  ring oscillator ,  bistable circuit ,  short circuit current ,  phase noise ,  *phase detector
Semi thesaurus term： analog to digital converter ,  CMOS process ,  *PLL ,  analog-to-digital converter ,  flip-flop circuit

Author keywords (3)： type-I ,  digital phase-locked loop ,  ring-based PLL

JST classification (2)： Oscillation circuits  (NC05020Y) ,  AD/DA conversion circuits  (NC05080M)

Reference (30)：

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• [2] F. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Communications, vol.28, no.11, pp.1849-1858, Nov. 1980. 10.1109/tcom.1980.1094619
• [3] H. Hedayati, W. Khalil, and B. Bakkaloglu, “A 1 MHz Bandwidth, 6 GHz 0.18 μm CMOS Type-I ΔΣ Fractional-N Synthesizer for WiMAX Applications (Vol 44, pg 3244, 2009),” IEEE J. Solid-State Circuits, vol.45, no.6, p.1256, 2010. 10.1109/jssc.2010.2048616
• [4] S. Shekhar, D. Gangopadhyay, E.-C. Woo, and D.J. Allstot, “A 2.4-GHz Extended-Range Type-I ΣΔ Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise,” IEEE Trans. Circuits Syst. II Express Briefs, vol.58, no.8, pp.472-476, 2011. 10.1109/tcsii.2011.2158752
• [5] A. Sharkia, S. Aniruddhan, S. Shekhar, and S. Mirabbasi, “A high-performance, yet simple to design, digital-friendly type-I PLL,” IEEE CICC2015, vol.2015-Novem, pp.5-8, 2015. 10.1109/cicc.2015.7338487

Terms in the title (8)： ループ ,  遅延 ,  補償 ,  ADC ,  サンプリング ,  位相検出器 ,  タイプ ,  PLL