Art

J-GLOBAL ID：201902287934833844   Reference number：19A0953835

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

誘導結合ThruChip Interfaceを用いた3Dチップ積層用のエスカレータネットワーク

Author (6)： Nomura Akio (Keio University) ,  Matsushita Yusuke (Keio University) ,  Kadomoto Junichiro (Keio University) ,  Matsutani Hiroki (Keio University) ,  Kuroda Tadahiro (Keio University) ,  Amano Hideharu (Keio University)
Material： International Journal of Networking and Computing (Web)  (IJNC (Web))
Volume： 8  Issue： 1  Page： 124-139(J-STAGE)  Publication year： 2018 
JST Material Number： U1549A  ISSN： 2185-2847  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *semiconductor chip ,  laminate structure ,  IC package ,  *performance evaluation ,  prototype ,  SiP ,  action and behavior
Semi thesaurus term： *3Dチップ ,  *エスカレータネットワーク ,  overhead ,  ピギーバック制御

JST classification (3)： Semiconductor integrated circuit  (NC03162T) ,  Network methods  (KA03040X) ,  Computer system development  (JD02010R)

Reference (20)：

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Terms in the title (3)： 誘導結合 ,  3D ,  エスカレータ