Art
J-GLOBAL ID:202002229781784542
Reference number:20A0842794
Study on Parasitic Calibration Method of C-C SAR-ADC Using γ-Estimation
γ推定を用いたC-C SAR-ADCの寄生容量補正法
Author (4):
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Material:
Issue:
ECT-20-027-033.035-040 電子回路研究会
Page:
43-47
Publication year:
Mar. 09, 2020
JST Material Number:
Z0924B
Document type:
Proceedings
Article type:
原著論文
Country of issue:
Japan (JPN)
Language:
JAPANESE (JA)
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Semi thesaurus term:
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
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Category name(code) classified by JST.
AD/DA conversion circuits
Reference (8):
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S. Thirunakkarasu and B. Bakkaloglu, ′′A radix-3 SAR analog-to-digital converter,′′ IEEE International Symposium on Circuits and Systems, Paris, 2010, pp.1460-1463.
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L. Chen, M. Rahman, S. Liu and N. Sun, ′′A fast radix-3 SAR analog-to-digital converter,′′ IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, 2013, pp.1148-1151.
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S.-W. M. Chen and R. W. Brodersen, ′′A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS′′, IEEE J. Solid-State Circuits, vol.41, no.12, pp.2669-2680, Dec. 2006.
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L. Cong, ′′Pseudo C-2C Ladder-Based Data Converter Technique′′, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.48, no.10, pp.927-929, Oct. 2001.
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関根 慧,松浦達治,岸田 亮,兵庫 明, 「整数容量比を用いたC-2C D/A変換器の設計手法」, 電気学会論文誌C(電子・情報・システム部門誌), 140巻, 2号, pp.194-203.
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