Art
J-GLOBAL ID：202102255864015962
Reference number：21A0453034
FPGA向き自己同期型パイプライン回路構成法
Author (5)：
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Material：
Volume：
2021
Issue：
ARC-243
Page：
Vol.2021-ARC-243,No.25,1-7 (WEB ONLY)
Publication year：
Jan. 18, 2021
JST Material Number：
U0451A
Document type：
Proceedings
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
JAPANESE (JA)
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Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
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General
Reference (8)：
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H. Terada, S. Miyata, and M. Iwata, “DDMP’s: SelfTimed Super-Pipelined Data-Driven Multimedia Processors,” Proc. IEEE, Vol.87, pp.282-295, Feb. 1999.
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S. Yoshikawa, S. Sannomiya, M. Iwata, and H. Nishikawa. “Pipeline Stage Level Simulation Method for Self-Timed Data-Driven Processor on FPGA,” 2020 8th International Electrical Engineering Congress, Vol. 1, pp1-4, Mar. 2020.
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C. J. Myers, “Asynchronous circuit design,” Univ. of Utah John Wiley & Sons, Inc., 2001.
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西川博昭,青木一浩,三宮秀次,宮城桂,岩田誠,宇津圭祐,石井啓之,“超低消費電力化データ駆動ネットワーキングシステムとその評価,” 電子情報通信学会論文誌 B, Vol.J96-B, No.6, pp.572-579, June 2013.
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三宮秀次,青木一浩,宮城桂,岩田誠,西川博昭,“超低消費電力化データ駆動ネットワーキングプロセッサ ULP-CUE の試作とその評価,” 情報処理学会論文誌コンピューティングシステム, Vol.6 No.1. pp.78-86, Jan. 2013.
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