Takahashi Yasuhiro

タカハシヤスヒロ | Takahashi Yasuhiro

Affiliation and department：
Other affiliations (2)：

Gifu University Graduate School of Engineering
Gifu University

Homepage URL (1)： http://www1.gifu-u.ac.jp/~yasut

Research field (5)： Communication and network engineering , Electronic devices and equipment , Information security , Computer systems , Medical systems

Research keywords (8)： Electronics circuit , アナログ電子回路 , Integrated circuit , VLSI design , LSI , 光通信システム , Adiabatic Logic , Memristor

Research theme for competitive and other funds (12)：

2022 - 2025 集積回路レイアウトの観点からみた暗号用デジタル断熱的論理回路の電流特性の解明
2020 - 2024 Beyond 5G 超大容量無線通信を支える次世代エッジクラウドコンピューティング基盤の研究開発
2017 - 2018 低電圧および低消費電力特性を有するサブスレッショルド断熱的論理の電力モデル構築
2015 - 2016 低電圧で作動する環境発電向けエネルギーリサイクル集積回路の設計
2012 - 2014 セキュアかつ低消費電力な断熱的論理回路の設計

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Papers (145)：

Inoue, T., Tsuchiya, A., Kishine, K., Takahashi, Y., Ito, D., Nakamura, M. A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Transactions on Circuits and Systems II: Express Briefs. 2024. 71. 5. 2514-2518
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura. A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectronics Journal. 2024. 145. 106120-106120
Koji Tominaga, Yasuhiro Takahashi. Low-Power, 25-Gb/s Active Voltage Current Feedback Transimpedance Amplifier in 65-nm CMOS. 2024 International Conference on Electronics, Information, and Communication (ICEIC). 2024
Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine. A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. 2024 International Conference on Electronics, Information, and Communication (ICEIC). 2024
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura. A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS). 2023

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MISC (3)：

Ultra Low-power Logic Circuit Using Adiabatic Switching Principle. The journal of the Institute of Electronics, Information and Communication Engineers. 2017. 100. 7. 642-647
高橋康宏. 省エネを目指すLSI設計とEMC: スマートカード用暗号LSIを事例に回路レベルの観点から. 電磁環境工学情報誌月刊EMC. 2017. 29. 12. 50-56
高橋康宏. 学会発表を通して学んだこと. 電子情報通信学会誌. 2003. 86. 2. 140

Patents (18)：

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Lectures and oral presentations (284)：

A Design of Wideband and Low-noise RGC-TIA
(電気学会研究会資料(Web) 2024)
A Study on Applying Dickson Rectifier to Adiabatic Logic Circuit
(電気学会研究会資料(Web) 2024)
A Design of PUF Circuit Using Adiabatic Logic
(電気学会研究会資料(Web) 2024)
A wide-band and Low-power Transimpedance Amplifier Using 65 nm CMOS
(電気学会研究会資料(Web) 2024)
Proposal for an AVCF-type low-power AFE TIA using 65-nm CMOS technology
(電気学会研究会資料(Web) 2023)

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Education (3)：

2002 - 2005 Yamagata University Graduate of Science and Engineering Division of System and Information Engineering
2000 - 2002 Yamagata University Graduate School of Science and Engineering Division of Electronic and Information
1996 - 2000 Yamagata University Faculty of Engineering Dept. of Electronic and Information Eng.

Professional career (1)：

Ph.D. (Yamagata University)

Work history (4)：

2020/01 - 現在高等研究院人工知能研究推進センター准教授(兼務)
2014/12 - 現在 Dept. of EECE, Faculty of Eng., Gifu University Associate Professor
2007/04/01 - 2014/11/30 Dept of EECE, Faculty of Eng., Gifu University Assistant Professor
2005/04/01 - 2007/03/31 Dept. of EEE, Faculty of Eng., Gifu University Research Associate

Committee career (13)：

2023/06 - 現在電子情報通信学会東海支部支部運営委員
2018/04 - 現在独立行政法人国際協力機構 (JICA) 東ティモール国立大学工学部能力向上プロジェクト国内支援委員
2018/01 - 現在電気学会電子回路研究専門委員会幹事
2024/04 - 2025/03 独立行政法人国際協力機構 (JICA) アドバイザー及び国内支援委員長
2017/06 - 2023/05 電子情報通信学会回路とシステム研究専門委員会(CAS) 専門委員

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Awards (3)：

2017/05 - 電子情報通信学会システムと信号処理サブソサイエティ貢献賞
2014/10/23 - IEEE IEEE IMPACT-EMAP 2014 Best poster award
2007/04/25 - LSI IP design Award

Association Membership(s) (4)：

日本数学史学会 , IEICE , IEEJ , IEEE

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