Art

J-GLOBAL ID：200902137265238448   Reference number：02A0816560

Test and Verification of VLSI. CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply.

VLSIのテストと検証 時間的に可変な電界供給の下での供給電流測定によるCMOS開放欠陥検出

Author (4)： HASHIZUME M (Univ. Tokushima, Tokushima-shi, JPN) ,  ICHIMIYA M (Univ. Tokushima, Tokushima-shi, JPN) ,  YOTSUYANAGI H (Univ. Tokushima, Tokushima-shi, JPN) ,  TAMESADA T (Univ. Tokushima, Tokushima-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E85-D  Issue： 10  Page： 1542-1550  Publication year： Oct. 01, 2002 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *VLSI ,...

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JST classification (1)： General  (NC03161C)

Reference (7)：

• SODEN, J. M. Electrical properties and detection methods for CMOS IC defects. Proc. European Test Conf. 1989, 159-167
• RENOVELL, M. Electrical analysis and modeling of floating gate faults. IEEE Trans. Comput. -Aided Des. Integrated Circuits & Syst. 1992, 11, 11, 1450-1458
• CHAMPAC, V. H. Electrical model of the floating gate defect in CMOS ICs : Implication on IDDQ testing. IEEE Trans. Comput. -Aided Des. Integrated Circuits & Syst. 1994, 13, 3, 359-369
• RAFIQ, S. Testing for floating gates defects in CMOS circuits. Proc. Seventh Asian Test Symposium. 1998, 228-236
• DE PAUL, I. Transient current testing based on current(charge) integration. Proc. IDDQ workshop. 1998, 26-30

Terms in the title (7)： VLSI ,  テスト ,  検証 ,  電界 ,  電流測定 ,  CMOS ,  欠陥検出