Art

J-GLOBAL ID：200902171112658646   Reference number：96A0353743

Implicit Representation and Manipulation of Binary Decision Diagrams.

二進決定ダイアグラムの暗示的表現と取扱い

Author (3)： YAMAUCHI H (Okayama Prefectural Univ., Soja-shi, JPN) ,  ISHIURA N (Osaka Univ., Suita-shi, JPN) ,  TAKAHASHI H (Okayama Prefectural Univ., Soja-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E79-A  Issue： 3  Page： 354-362  Publication year： Mar. 1996 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： logical function ,...

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JST classification (1)： Logic circuits  (NC05070B)

Reference (6)：

• AKERS, S. B. Binary decision diagrams. IEEE Trans. Comput. 1978, C-27, 6, 509-516
• BRYANT, R. E. Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. 1986, C-35, 8, 677-691
• BURCH, J. R. Sequential circuit verification using symbolic model checking. Proc. ACM/IEEE 27th DAC. 1990, 46-51
• CHOI, H. Test generation for sequential circuits based on Boolean function manipulation. IEICE Trans. Fundamentals. 1993, J76-A, 6, 835-843
• ISHIURA, N. Minimization of binary decision diagrams based on exchanges of variables. Proc. IEEE ICCAD-91. 1991, 472-475

Terms in the title (4)： 決定ダイアグラム ,  暗示 ,  表現 ,  取扱い