Art

J-GLOBAL ID：200902201071910650   Reference number：09A1258101

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs

LUT型FPGAの深さ最適テクノロジーマッピングに対する効率的なカット計数ヒューリスティックス

Author (2)： TAKATA Taiga (Kyushu Univ., Fukuoka-shi, JPN) ,  MATSUNAGA Yusuke (Kyushu Univ., Fukuoka-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E92-A  Issue： 12  Page： 3268-3275  Publication year： Dec. 01, 2009 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *FPGA ,  look-up table ,  network ,  equivalent transformation ,  depth ,  cut-set ,  direct product ,  Time ,  computer algorithm ,  counting technique ,  high speed ,  heuristics ,  experiment ,  optimization method ,  optimum design ,  Decision Making ,  possibility ,  evaluation experiment ,  Boolean Networks
Semi thesaurus term： network using the Boolean function ,  execution time ,  *technology mapping ,  top down ,  reconfigurability

JST classification (2)： Special-purpose arithmetic and control units  (JC04030Y) ,  CAD,CAM  (JE10000A)

Reference (14)：

• CONG, J. Flowmap : An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 1994, 13, 1, 1-12
• CONG, J. On area/depth trade-off in lut-based fpga technology mapping. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 1994, 2, 2, 213-218
• CONG, J. Simultaneous depth and area minimization in lut-based fpga mapping. Proc. ACM 3rd Int'l Symp. on FPGA, 1995. 1995, 68-74
• CONG, J. Cut ranking and pruning : Enabling a general and efficient fpga mapping solution. Proc. FPGA'99. 1999, 29-35
• CHEN, D. Daomap : A depth-optimal area optimization mapping algorithm for fpga designs. Proc. ICCAD'04. 2004, 752-759

Terms in the title (5)： LUT ,  FPGA ,  テクノロジーマッピング ,  計数 ,  ヒューリスティックス