Art

J-GLOBAL ID：200902204867399719   Reference number：06A0698323

Redundant Design for Wallace Multiplier

Wallace乗算器の冗長設計

Author (2)： NAMBA Kazuteru (Chiba Univ., Chiba-shi, JPN) ,  ITO Hideo (Chiba Univ., Chiba-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E89-D  Issue： 9  Page： 2512-2524  Publication year： Sep. 01, 2006 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *multiplier ,...
Semi thesaurus term： bit-slice ,...

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JST classification (2)： Arithmetic systems  (JC02020Z) ,  Logic circuits  (NC05070B)

Reference (9)：

• HIRASE, J. Yield increase of VLSI after redundancy-repairing. Proc. Tenth Asian Test Symp., Nov. 2001. 2001, 353-358
• OTTAVI, M. Yield evaluation methods of SRAM arrays : A comparative study. Proc. IEEE Instrum. Measurement Tech. Conf., May 2004. 2004, 2, 1525-1530
• SCHOBER, V. Memory built-in self-repair using redundant words. Int'l Test Conf., 2001. 2001, 995-1001
• COWAN, B. On-chip repair and an ATE independent fusing methodology. IEEE Int. Test Conf., 2002. 2002, 178-186
• ZORIAN, Y. Embedded-memory test and repair : Infrastructure IP for SoC yield. IEEE Des. Test Comput. 2003, 20, 3, 58-65

Terms in the title (3)： 乗算器 ,  冗長 ,  設計