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J-GLOBAL ID：200902205406177273   Reference number：06A0412197

Vertical Double-Gate MOSFET Device Technology

縦型ダブルゲートMOSFETデバイス技術

Author (5)： MASAHARA MEISHOKU (産業技術総合研) ,  LIU Yongxun (産業技術総合研) ,  ENDO KAZUHIKO (産業技術総合研) ,  MATSUKAWA TAKASHI (産業技術総合研) ,  SUZUKI EIICHI (産業技術総合研)
Material： 電気学会論文誌 C  (IEEJ Transactions on Electronics, Information and Systems)
Volume： 126  Issue： 6  Page： 702-707  Publication year： Jun. 01, 2006 
JST Material Number： S0810A  ISSN： 0385-4221  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： *MOSFET ,...

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JST classification (1)： Transistors  (NC03070N)

Reference (10)：

• (1) T. Sekigawa and Y. Hayashi : “Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate”, Solid-State Electron, Vol. 27, p. 827 (1984)
• (2) D. Hisamoto, W. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T. King, J. Bokor, and C. Hu : “A folded-channel MOSFET for deep-sub-tenth micron era”, Tech. Dig. IEDM, pp. 1032-1034, San Francisco, USA (1998-12)
• (3) M. Masahara, T. Matsukawa, K. Ishii, Y. Liu, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki : “15-nm-thick Si channel wall vertical double-gate MOSFET”, Tech. Dig. IEDM, pp. 949-951, San Francisco, USA (2002-12)
• (4) J. M. Hergenrother, et al. : “The vertical replacement-gate (VRG) MOSFET”, Tech. Dig. IEDM, pp. 73-75, Washington, USA (1999-12)
• (5) M. Masahara, Y. X. Liu, S. Hosokawa, T. Matsukawa, K. Ishii, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki : “Ultrathin channel vertical double-gate MOSFET fabricated by using ion-bombardment-retarded Etching”, IEEE Trans. Electron Devices, Vol. 51, No. 12, p. 2078 (2004)

Terms in the title (2)： 縦型 ,  ダブルゲートMOSFET