Rchr
J-GLOBAL ID：200901077113076950
Update date: Sep. 02, 2024
Matsukawa Takashi
マツカワ タカシ | Matsukawa Takashi
Affiliation and department：
National Institute of Advanced Industrial Science and Technology
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Homepage URL (1)：
http://www.aist.go.jp/RESEARCHERDB/cgi-bin/worker_detail.cgi?call=namae&rw_id=T34207766
Research field (1)：
Electronic devices and equipment
Research theme for competitive and other funds (2)：
2014 - 2017 CMOS FinFET technologies toward low-cost terahertz generation for safe and secure society
1997 - 1999 Fabrication of semiconductor nano-scale structures and control of its electrical characteristics by means of quantum doping
Papers (210)：
Md Mehdee Hasan Mahfuz, Motohiro Tomita, Shuhei Hirao, Kazuaki Katayama, Kaito Oda, Takashi Matsukawa, Takeo Matsuki, Takanobu Watanabe. Designing a bileg silicon-nanowire thermoelectric generator with cavity-free structure. Japanese Journal of Applied Physics. 2021. 60. SB. SBBF07-SBBF07
Katsuki Abe, Kaito Oda, Motohiro Tomita, Takeo Matsuki, Takashi Matsukawa, Takanobu Watanabe. 4-4 Effect of Unit-cell Arrangement on Performance of Multi-stage-planar Cavity-free Unileg Thermoelectric Generator Using Silicon Nanowires. 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). 2020
Kimihiko Kato, Tetsufumi Tanamoto, Takahiro Mori, Yukinori Morita, Takashi Matsukawa, Mitsuru Takenaka, Shinichi Takagi. Impact of Switching Voltage on Complementary Steep-Slope Tunnel Field Effect Transistor Circuits. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2020. 67. 9. 3876-3882
Tianzhuo Zhan, Shuaizhe Ma, Zhicheng Jin, Hiroki Takezawa, Kohei Mesaki, Motohiro Tomita, Yen-Ju Wu, Yibin Xu, Takashi Matsukawa, Takeo Matsuki, et al. Effect of the Thermal Boundary Resistance in Metal/Dielectric Thermally Conductive Layers on Power Generation of Silicon Nanowire Microthermoelectric Generators. ACS Applied Materials & Interfaces. 2020. 12. 30. 34441-34450
Kimihiko Kato, Takahiro Mori, Yukinori Morita, Takashi Matsukawa, Mitsuru Takenaka, Shinichi Takagi. Source engineering for bilayer tunnel field-effect transistor with hetero tunnel junction: thickness and impurity concentration. APPLIED PHYSICS EXPRESS. 2020. 13. 7
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MISC (54)：
TCAD Simulation of C-TFET Circuit with Drain Offset Structure. 2017. 41. 25. 21-24
Oxygen etching technology for 3D Ge channel transistors. 2016. 80. 49-52
SRAM PUF using Polycrystalline Silicon Channel FinFET and Its Evaluation. 2016. 40. 24. 83-87
MASAHARA Meishoku, ENDO Kazuhiko, OUCHI Shin-ichi, MATSUKAWA Takashi, Liu Yongxun, MIGITA Shinji, MIZUBAYASHI Wataru, MORITA Yukinori, OTA Hiroyuki. Multigate FinFET Device and Circuit Technology for 10nm and Beyond. Technical report of IEICE. ICD. 2014. 114. 13. 77-82
Suzuki Keijiro, Tanizawa Ken, Matsukawa Takashi, Cong Guangwei, Kim Sang-Hun, Suda Satoshi, Ohno Morifumi, Chiba Tadashi, Tadokoro Hirofumi, Yanagihara Masashi, et al. C-3-75 Ultra-Compact Si-Wire 8×8 PILOSS Switch. Proceedings of the IEICE General Conference. 2014. 2014. 1. 230-230
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Professional career (1)：
博士(工学) (早稲田大学)
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