Art

J-GLOBAL ID：200902221611468812   Reference number：05A0842281

High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition

非対称信号遷移の差分論理を用いる高速ディジタル回路設計

Author (3)： MORIMOTO Masao (Kobe Univ., Kobe-shi, JPN) ,  NAGATA Makoto (Kobe Univ., Kobe-shi, JPN) ,  TAKI Kazuo (Kobe Univ., Kobe-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E88-C  Issue： 10  Page： 2001-2008  Publication year： Oct. 01, 2005 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *combinational circuit ,...
Semi thesaurus term： 差分論理回路

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JST classification (1)： Logic circuits  (NC05070B)

Reference (12)：

• GROTJOHN, T. A. Sample-set differential logic (SSDL) for complex high-speed VLSI. IEEE J. Solid-State Circuits. 1986, 21, 4, 367-369
• WU, C.-Y. Latched CMOS differential logic (LCDL) for complex high-speed VLSI. IEEE J. Solid-State Circuits. 1991, 26, 9, 1324-1328
• PARK, J. Current sensing differential logic : A CMOS logic for high reliability and flexibility. IEEE J. Solid-State Circuits. 1999, 34, 6, 904-908
• PFENNINGS, L. C. M. G. Differential split-level CMOS logic for subnanosecond speeds. IEEE J. Solid-State Circuits. 1985, 20, 5, 1050-1055
• PRETORIUS, J. A. Latched domino CMOS logic. IEEE J. Solid-State Circuits. 1986, 21, 4, 514-522

Terms in the title (6)： 非対称 ,  遷移 ,  差分 ,  論理 ,  ディジタル回路 ,  設計