Art

J-GLOBAL ID：200902246112866320   Reference number：06A0152015

A Statistical Quality Model for Delay Testing

遅延試験用の統計的品質モデル

Author (5)： SATO Yasuo (Semiconductor Technol. Academic Res. Center, Yokohama-shi, JPN) ,  HAMADA Shuji (Semiconductor Technol. Academic Res. Center, Yokohama-shi, JPN) ,  MAEDA Toshiyuki (Semiconductor Technol. Academic Res. Center, Yokohama-shi, JPN) ,  TAKATORI Atsuo (Semiconductor Technol. Academic Res. Center, Yokohama-shi, JPN) ,  KAJIHARA Seiji (Kyushu Inst. of Technol., Iizuka-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E89-C  Issue： 3  Page： 349-355  Publication year： Mar. 01, 2006 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *VLSI ,...

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JST classification (1)： General  (NC03161C)

Reference (13)：

• SEGURA, J. Parametric failures in CMOS ICs-A defect-based analysis. Proc. IEEE International Test Conference, 2002. 2002, 90-99
• KRSTIC, A. Delay fault testing for VLSI circuits. 1998
• YANG, K. TranGen : A SAT-based atpg for path-oriented transition faults. Proc. Asian and South Pacific Design Automation Conference, Jan. 2004. 2004, 92-97
• PARK, E. S. Statistical delay fault coverage and defect level for delay faults. Proc. IEEE International Test Conference, 1988. 1988, 160-167
• PARK, E. S. Delay testing quality in timing-optimized designs. Proc. IEEE International Test Conference, 1991. 1991, 168-176

Terms in the title (4)： 遅延 ,  試験 ,  統計 ,  品質モデル