Art

J-GLOBAL ID：200902246565957970   Reference number：03A0868079

An Efficiently Self-Reconstructing Array System Using E-1 1/2-Track Switches

E-1(1/2)-トラックスイッチを使用した効率的な自己再構成アレイシステム

Author (2)： HORITA T (Polytechnic Univ., Sagamihara-shi, JPN) ,  TAKANAMI I (Ichinoseki National Coll. Technol., Ichinoseki-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E86-D  Issue： 12  Page： 2743-2752  Publication year： Dec. 01, 2003 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *parallel computer ,...
Semi thesaurus term： 耐故障性

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JST classification (2)： Digital computer systems in general  (JC02010O) ,  Other digital computer systems  (JC02050G)

Reference (23)：

• TURNBULL, J. R. An analysis of the interconnection problem for WSI. Wafer Scale Integration. 1986, 24-30
• MANGIR, T. E. Fault-tolerant design for VLSI : Effect of interconnection requirements on yield improvement of VLSI designs. IEEE Trans. Comput. 1982, C-31, 7, 609-615
• ROSENBERG, A. L. The diogenes approach to testable fault-tolerant arrays of processors. IEEE Trans. Comput. 1983, C-32, 10, 902-910
• SAMI, M. Reconfigurable architectures for VLSI processing arrays. Proc. IEEE, May. 1986, 712-722
• NEGRINI, R. Fault-tolerance through reconfiguration of VLSI and WSI arrays. 1989

Terms in the title (4)： トラック ,  自己 ,  再構成 ,  アレイ