Art

J-GLOBAL ID：200902285932789376   Reference number：08A1241420

On Fault Testing for Reversible Circuits

可逆回路における故障検出

Author (3)： TAYU Satoshi (Tokyo Inst. of Technol., Tokyo, JPN) ,  ITO Shigeru (Tokyo Inst. of Technol., Tokyo, JPN) ,  UENO Shuichi (Tokyo Inst. of Technol., Tokyo, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E91-D  Issue： 12  Page： 2770-2775  Publication year： Dec. 01, 2008 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *fault detection ,  stuck-fault ,  *reciprocal circuit ,  *circuit test ,  completeness ,  satisfiability problem ,  NP complete problem ,  Boolean function
Semi thesaurus term： テストベクトル

JST classification (2)： Measurement,testing and reliability of solid-state devices  (NC03040G) ,  Logic circuits  (NC05070B)

Reference (7)：

• BENNETT, C. Logical reversiblity of computation. IBM J. Res. Dev. 1973, 17, 525-532
• CHAKRABORTY, A. Synthesis of reversible circuits for testing with universal test set and c-testability of reversible iterative logic array. Proc. 18th International Conference on VLSI Design, 2005. 2005
• LANDAUER, R. Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 1961, 5, 183-191
• MERKLE, R. Two types of mechanical reversible logic. Nanotechnology. 1993, 4, 114-131
• NIELSEN, M. Quantum Computation and Quantum Information. 2000

Terms in the title (2)： 可逆回路 ,  故障検出