Art

J-GLOBAL ID：200902294347771584   Reference number：04A0743959

Self-Reconfiguring of 1(1/2)-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit

単純な組込回路による一行と一列に予備を備えた1・1/2トラックスイッチ・メッシュアレイの自己再構成

Author (1)： TAKANAMI I (Ichinoseki National Coll. Technol., Ichinoseki-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E87-D  Issue： 10  Page： 2318-2328  Publication year： Oct. 01, 2004 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *self correcting computer ,...

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JST classification (1)： Other digital computer systems  (JC02050G)

Reference (21)：

• KUNG, S. Y. Fault-tolerant array processors using single-track switches. IEEE Trans. Comput. 1989, 38, 4, 501-514
• MANGIR, T. E. Fault-tolerant design for VLSI : Effect of interconnection requirements on yield improvement of VLSI designs. IEEE Trans. Comput. 1982, C-31, 7, 609-615
• LEIGHTON, T. Wafer-scale integration of systolic arrays. IEEE Trans. Comput. 1985, C-34, 5, 448-461
• LAM, C. W. H. A study of two approaches for reconfiguring fault-tolerant systolic arrays. IEEE Trans. Comput. 1989, 38, 6, 833-844
• KIM, J. H. On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement. IEEE Trans. Comput. 1989, 38, 4, 515-525

Terms in the title (3)： 組込 ,  自己 ,  再構成