Art

J-GLOBAL ID：201002254315981039   Reference number：10A1165160

SAR ADC Architecture with Digital Error Correction

ディジタル誤り訂正によるSAR ADCアーキテクチャー

Author (9)： HOTTA Masao (Tokyo City Univ., Tokyo, JPN) ,  KAWAKAMI Masayuki (Tokyo City Univ., Tokyo, JPN) ,  KOBAYASHI Haruo (Gunma Univ., Kiryu, JPN) ,  SAN Hao (Tokyo City Univ., Tokyo, JPN) ,  TAKAI Nobukazu (Gunma Univ., Kiryu, JPN) ,  MATSUURA Tatsuji (Semiconductor Technol. Academic Res. Center, Yokohama, JPN) ,  ABE Akira (Semiconductor Technol. Academic Res. Center, Yokohama, JPN) ,  YAGI Katsuyoshi (Semiconductor Technol. Academic Res. Center, Yokohama, JPN) ,  MORI Toshihiko (Semiconductor Technol. Academic Res. Center, Yokohama, JPN)
Material： IEEJ Transactions on Electrical and Electronic Engineering  (IEEJ Trans Electr Electron Eng)
Volume： 5  Issue： 6  Page： 651-659  Publication year： Nov. 2010 
JST Material Number： W1854A  ISSN： 1931-4973  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)

Thesaurus term： error correction ,  digital system ,  *analog to digital converter ,  register ,  computer architecture ,  comparator ,  circuit design
Semi thesaurus term： successive approximation register

JST classification (1)： AD/DA conversion circuits  (NC05080M)

Reference (9)：

• CASIER, H. Technology consideration for automotive. Proceedings of ESSCIRC, Leuven, Belgium, September, 2004. 2004, 37-41
• ISSCC Short Course. Automotive Technology and Circuits, San Francisco, February, 2005. 2005
• KUTTNER, F. A 1.2V 10b 20 MS/S non-binary successive approximation ADC in O.13μm CMOS. Technical Digest of ISSCC, San Francisco, February, 2002. 2002
• HESENER, M. A 14b 40 MS/s redundant SAR ADC with 480 MHz clock in 0.13μm CMOS. Technical Digest of ISSCC, San Francisco, February, 2007. 2007
• HOTTA, M. SAR ADC architecture with digital error correction. Technical Digest of Analog VLSI Workshop 2006, Hangzhou, China, November. 2006

Terms in the title (5)： ディジタル ,  誤り訂正 ,  SAR ,  ADC ,  アーキテクチャー