Art

J-GLOBAL ID：201202211434300809   Reference number：12A0273767

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks

スイッチブロックなしの新しいメモリベース再構成可能アーキテクチャのための物理設計法

Author (6)： NAKAMURA Masatoshi (Graduate School of Information Sciences, Hiroshima City Univ.) ,  INAGI Masato (Graduate School of Information Sciences, Hiroshima City Univ.) ,  TANIGAWA Kazuya (Graduate School of Information Sciences, Hiroshima City Univ.) ,  HIRONAKA Tetsuo (Graduate School of Information Sciences, Hiroshima City Univ.) ,  SATO Masayuki (Taiyo Yuden Co., Ltd) ,  ISHIGURO Takashi (Taiyo Yuden Co., Ltd)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E95-D  Issue： 2  Page： 324-334 (J-STAGE)  Publication year： 2012 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： Physics ,  design ,  PLD ,  *arrangement ,  FPGA ,  circuit design ,  *reconfigurable architectures
Semi thesaurus term： cost function ,  programmable logic device ,  *routing algorithm ,  *reconfigurable architecture ,  *物理設計

JST classification (1)： General-purpose arithmetic and control units  (JC04020N)

Reference (15)：

• BROWN, S. Field-Programmable Gate Arrays. 1992
• MARRAKCHI, Z. FPGA Interconnect topologies exploration. Int. J. Reconfigurable Computing. 2009, 2009, 1-13
• HIRAKAWA, N. A PLD Architecture for high performance computing. Proc. 2008 Int. Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. 2008, 35-42
• TANIGAWA, K. Memory array based PLD architecture for high-density logic mapping-Implementation of first demo chip. Proc. COOL chips XIV, poster 1, 2011. 2011
• BETS, V. VPR : A new packing, placement and routing tool for FPGA research. Proc. IEEE FPL 1997. 1997, 213-222

Terms in the title (2)： 再構成可能アーキテクチャ ,  物理設計