Art

J-GLOBAL ID：201402253752266988   Reference number：14A0618772

An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies

ナノメータテクノロジーの複数入力ゲート用のオーバーシュート効果の効果的モデル

Author (5)： DING Li (Graduate School of Information, Production and Systems, Waseda Univ.) ,  HUANG Zhangcai (Graduate School of Information, Production and Systems, Waseda Univ.) ,  KUROKAWA Atsushi (Graduate School of Information, Production and Systems, Waseda Univ.) ,  WANG Jing (Graduate School of Information, Production and Systems, Waseda Univ.) ,  INOUE Yasuaki (Graduate School of Information, Production and Systems, Waseda Univ.)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E97.A  Issue： 5  Page： 1059-1074 (J-STAGE)  Publication year： 2014 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *overshoot ,  *nanotechnology ,  *modeling ,  Electronics ,  delay characteristic ,  electric power consumption ,  inverter ,  gate (semiconductor) ,  pulse modulation ,  SPICE program ,  CMOS technology
Semi thesaurus term： NOR gate ,  PTM ,  gate delay

JST classification (2)： Manufacturing technology of solid-state devices  (NC03030V) ,  Logic circuits  (NC05070B)

Reference (22)：

• [1] Z. Huang, A. Kurokawa, Y. Yang, H. Yu, and Y. Inoue, “Modeling the influence of input-to-output coupling capacitance on CMOS inverter delay,” IEICE Trans. Fundamentals, vol.E89-A, no.4, pp.840-846, April 2007.
• [2] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, “Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.29, no.2, pp.250-260, Feb. 2010.
• [3] L. Ding, Z. Huang, M. Jiang, A. Kurokawa, and Y. Inoue, “Modeling the overshooting effect of multi-input gate in nanometer technologies,” MWSCAS2011, pp.1-4, Seoul, Aug. 2011.
• [4] L. Bisdounis, “Analytical modeling of overshooting effect in sub-100nm CMOS inverters,” J. Circuits, Systems, and Computers, vol.20, no.7, pp.1303-1321, Nov. 2011.
• [5] L.M. Brocco, S.P. McCormick, and J. Allen, “Macromodeling CMOS circuits for timing simulation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.7, no.12, pp.1237-1249, Dec. 1988.

Terms in the title (4)： ナノメータテクノロジー ,  ゲート ,  シュート ,  モデル