Art

J-GLOBAL ID：201502292289633219   Reference number：15A0242998

Normally-Off Computing with Perpendicular STT-MRAM

垂直磁化型STT-MRAMを用いたノーマリオフコンピューティング

Author (6)： NOGUCHI HIROKI (東芝 研開セ) ,  IKEGAMI KAZUTAKA (東芝 研開セ) ,  SHIMOMURA NAOHARU (東芝 研開セ) ,  TANAMOTO TETSUFUMI (東芝 研開セ) ,  ITO JUN'ICHI (東芝 研開セ) ,  FUJITA SHINOBU (東芝 研開セ)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 114  Issue： 346(CPSY2014 85-121)  Page： 107-112  Publication year： Nov. 24, 2014 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： electron spin ,  *cache memory ,  error correcting code ,  tunnel junction ,  perpendicular magnetization ,  *nonvolatile memory ,  spin torque
Semi thesaurus term： error correcting code ,  MTJ

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (30)：

• S. Borkar and A. A. Chien, "The future of microprocessor," Communications of the ACM, vol. 54, no. 5, pp. 67-77, May 2011.
• S. Rusu et al., "Ivytown: a 22nm 15-core enterprise Xeon® processor family," ISSCC Dig. Tech. Papers, pp. 102-103, Feb. 2014.
• E. J. Fluhr et al., "POWER8^TM: a 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth," ISSCC Dig. Tech. Papers, pp. 96-97, Feb. 2014.
• F. Hamzaoglu et al., "A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology," ISSCC Dig. Tech. Papers, pp. 230-231, Feb. 2014.
• H. Yoda et al., "Progress of STT-MRAM technology and the effect on normally-off computing systems," IEDM Tech. Dig., pp. 259-262, Dec. 2012.

Terms in the title (2)： 垂直磁化 ,  STT-MRAM